1. Field of the Invention
The present invention relates to an overcurrent protection circuit for a voltage regulator.
2. Description of the Related Art
FIG. 3 shows a configuration of a conventional overcurrent protection circuit for a voltage regulator. A reference voltage source 101 supplies a constant-voltage Vref to an inverted input terminal of an error amplifier 102. An output of the error amplifier 102 is connected to a gate of a PMOS output driver transistor 105, and is also connected to a gate of a first PMOS sense transistor 106 and a drain of a PMOS transistor 107 of an overcurrent protection circuit 103. A source of the PMOS output driver transistor 105 is connected to an input terminal IN and a drain of the same is connected to an output terminal OUT. A load resistor 114, a capacitor 113 and a voltage dividing circuit 104 consisting of resistors 111 and 112 are connected to the output terminal OUT. The voltage dividing circuit 104 supplies a divided voltage of an output voltage VOUT to a non-inverted input terminal of the error amplifier 102.
The overcurrent protective circuit 103 is constituted by the first PMOS sense transistor 106, the PMOS transistor 107, an NMOS transistor 108 and resistors 109 and 110. In the case in which the PMOS output driver transistor 105 and the first PMOS sense transistor 106 are both operating in a saturated state, a current proportional to a current flowing to the PMOS output driver transistor 105 flows to the first PMOS sense transistor 106. In this case, the proportion is substantially equal to a transistor size ratio of the transistors.
The case will be considered in which the PMOS output driver transistor 105 and the first PMOS sense transistor 106 are operating in the saturated state. If an amount of current supplied by the PMOS output driver transistor 105 to the load 114 is little, a current flowing to the first PMOS sense transistor 106 is small in proportion to it. Thus, a voltage difference generated at both ends of the resistor 109 is also small and the NMOS transistor 108 is in a non-conduction state. Therefore, since a current does not flow to the NMOS transistor 108, a voltage difference is not generated at both ends of the resistor 110 and the PMOS transistor 107 is also in a non-conduction state.
However, when a current supplied by the PMOS output driver transistor 105 to the load 114 increases, a current flowing to the first PMOS sense transistor 106 also increases in proportion to it and a voltage generated at both ends of the resistor 109 also increases. Thus, the NMOS transistor 108 in a conductive state. When the NMOS transistor 108 becomes conductive and a voltage difference generated at both the ends of the resistor 110 increases, the PMOS transistor 107 conducts to increase a gate voltage of the PMOS output driver transistor 105. Thus, a driving ability of the PMOS output driver transistor 105 decreases and an output voltage OUT falls. FIG. 4 shows this state. In this way, elements are prevented from being destroyed by an overload current.
In the circuit shown in FIG. 3, when a difference between the input voltage VIN and the output voltage VOUT is small, the PMOS output driver transistor 105 is unsaturated. However, the first PMOS sense transistor 106 is operating in the saturated state. Then, since the operating states of the PMOS output driver transistor 105 and the first PMOS sense transistor 106 are different, a ratio of currents flowing to the transistors is different from a transistor size ratio thereof. A current flowing to the first PMOS sense transistor 106 is larger than a current value that is found from the transistor size ratio of the PMOS output driver transistor 105 and the first PMOS sense transistor 106 and a current flowing to the PMOS output driver transistor 105.
That is, when the PMOS output driver transistor is unsaturated, a current flowing to the first PMOS sense transistor 106 increases even if a load current is small. At this time, as described above, the PMOS transistor 107 conducts to increase a gate voltage of the PMOS output driver transistor 105. Thus, there are disadvantages in that an abnormal operation occurs in the overcurrent protection circuit 103 such as a decreasing driving ability of the PMOS output driver transistor 105 and the fall of an output voltage OUT is more conspicuous compared with a case in which the overcurrent protection circuit 103 is not provided. FIG. 5 shows this state.
In addition, even in the case in which a difference between the input voltage VIN and the output voltage VOUT is large and both the PMOS output driver transistor 105 and the first PMOS sense transistor 106 are both operating in the saturated state, since source-to-drain voltages of the transistors are different from each other, a ratio of currents flowing to them is different from a transistor size ratio thereof due to an influence of channel length modulation. As a result, there is a disadvantage in that a load current under which the overcurrent protection operates becomes inaccurate.
In the present invention, operating states of a PMOS output driver transistor and a first PMOS sense transistor are always made the same to set a ratio of currents flowing to both the transistors equal to a transistor size ratio. Consequently, the present invention solves the problem that a load current under which an overcurrent protection operates becomes inaccurate by a decrease in an output voltage due to an abnormal operation of an overcurrent protection circuit in the case in which a difference of an input voltage VIN and an output voltage VOUT is small, and due to the influence of channel length modulation in the case in which the difference of an input voltage VIN and an output voltage VOUT is large.